The present invention relates to integrated circuit technology. More particularly, the present invention relates to programmable logic circuits, such as FPGAs, and particularly flash-based programmable logic circuits. The present invention addresses how to efficiently provide static control signals to circuit elements external to the FPGA fabric without compromising the bandwidth of the dynamic signal path.
An FPGA integrated circuit includes many circuit elements in addition to the FPGA fabric that require bits to control their functionality. A typical example is a general purpose I/O cell which typically has three dynamic signals (i.e., input, output, enable) that must be capable of being driven by a net from and to the FPGA.
Accompanying these signals are usually several control signals (which may number ten or more) that typically do not need connectivity to a net but need to be statically set. Such signals include those to configure the I/O standard being implemented (e.g. HSTL, PCI, etc.), and the enabling of delay elements in the input path. As the element gets more complex, the number of required static control signals can become much larger than the number of dynamic signals. An example of this is a SerDes with physical coding sub-layer (PCS) circuitry which may require static control signals for idle, align and stuff characters (16 bits each), SerDes drive, pre-emphasis and equalization control, and PCS data path selection.
As the number of signals necessary to configure circuit elements outside of the FPGA fabric increases, so does the number of signal lines needed to carry those signals. At some point, the bandwidth of the dynamic signal path is affected, since there is a physical limit to the number of conductors that can pass outside of the FPGA fabric. The present invention addresses how to efficiently provide those control signals to the circuit elements without compromising the bandwidth of the dynamic signal path.
Referring first to FIG. 1, a block diagram illustrates a prior-art arrangement for configuring circuit elements external to an FPGA array in an integrated circuit. Integrated circuit 10 includes an FPGA array 12 and also includes a group of external circuit elements 14. As is known in the art, the group of external circuit elements 14 may include circuit elements that need to be configured by static signals to control aspects of their operation. Representative ones of such configurable circuit elements are represented by small squares 16, 18, 20, 22, 24, 26, 28, and 30. Persons of ordinary skill in the art will appreciate that such configurable circuit elements can be as simple as an I/O or as complex as a PCS or a processor.
The configurable circuit elements 16, 18, 20, 22, 24, 26, 28, and 30 are controlled, respectively, by configuration bits 32, 34, 36, 38, 40, 42, 44, and 46, distributed throughout the FPGA array 12. Thus configuration bit 32 is shown coupled to external configurable circuit element 16, configuration bit 34 is shown coupled to external configurable circuit element 18, and so forth. The configuration bits may comprise non-volatile memory cells such as flash memory cells.
As will be apparent to persons of ordinary skill in the art examining FIG. 1, an individual conductor is needed to make each of the connections, thus requiring eight conductors running from the FPGA 12 to the external circuit elements 14 for making the eight connections in the illustrative example of FIG. 1.
In real-world integrated circuits that implement the above-described scheme, the number of connections between configuration bits in the FPGA array and the external circuit elements becomes exceedingly large as the size of the integrated circuit (i.e., gate count and number of I/O and other circuits external to the FPGA) increases. In addition, as the control requirements proliferate, there may not be enough physical room or architectural bandwidth to efficiently route one signal per control bit to the external element without compromising the effective bandwidth of the dynamic signals. At some point, the number of such conductors becomes unreasonably large and can become a critical design issue. The present invention presents a solution to this problem.
The configurable circuit elements 16, 18, 20, 22, 24, 26, 28, and 30 are controlled, respectively, by configuration bits 32, 34, 36, 38, 40, 42, 44, and 46, distributed throughout the FPGA fabric 12. Thus configuration bit 32 is shown coupled to external configurable circuit element 16, configuration bit 34 is shown coupled to external configurable circuit element 18, and so forth. The configuration bits may comprise non-volatile memory cells such as flash memory cells.
As will be apparent to persons of ordinary skill in the art examining FIG. 1, an individual conductor is needed to make each of the connections, thus requiring eight conductors running from the FPGA 12 to the external circuit elements 14 for making the eight connections in the illustrative example of FIG. 1.
In real-world integrated circuits that implement the above-described scheme, the number of connections between configuration bits in the FPGA fabric and the external circuit elements becomes exceedingly large as the size of the integrated circuit (i.e., gate count and number of I/O and other circuits external to the FPGA) increases. In addition, as the control requirements proliferate, there may not be enough physical room or architectural bandwidth to efficiently route one signal per control bit to the external element without compromising the effective bandwidth of the dynamic signals. At some point, the number of such conductors becomes unreasonably large and can become a critical design issue. The present invention presents a solution to this problem.